The subject matter described herein relates generally to the field of semiconductor device manufacturing, particularly to a chuck for mounting semiconductor wafers during processing and a method of semiconductor processing, and more particularly to a chuck and method of processing that limit unwanted exposure of unprocessed portions of the wafer to processing chemicals while securing the wafer in a manner suitable for noncontact combinatorial wafer processing.
Semiconductor electronic devices are found in virtually every segment of the modern economy. Continual efforts are made to improve such devices, to develop new, better and cheaper devices, to improve the materials used in such devices and to improve manufacturing processes. There is an on-going need in the art for improvements in all aspects related to semiconductor device design, manufacturing and use.
A typical semiconductor device includes numerous different materials, interfaces between materials and subsystems whose electrical, thermal, chemical and mechanical properties affect the overall performance of the device. Different semiconductor materials with different dopants and doping levels are typically present, along with various conductors and insulators, all in various geometric configurations with numerous interfacial regions where such materials come into contact, may blend to form alloys or distinct compounds. Additional complexity can arise from effects of processing. Thus, in designing such devices, or striving to improve the materials and/or manufacturing processes, it is important to know the properties of such materials and interfaces, how such properties are expected to change in response to contemplated changes in materials, geometry and/or processing, and to improve processing equipment and techniques to reduce unwanted exposures of device locations to undesirable chemicals.
Techniques for conducting dozens or even hundreds of experiments in parallel have been developed, and continue to be developed, under the general label “combinatorial processing.” These techniques obviously speed up R&D by a tremendous factor, allowing numerous tests to be conducted, and data collected, concurrently. One recent discussion of combinatorial techniques applied to materials science can be found in “Combinatorial Materials Science” by B. Narasimhan et al (eds)., Wiley-Interscience (2007). In particular, various materials, geometries and processing conditions for the manufacture of semiconductor devices can be tested in parallel, exemplified by the specific applications of combinatorial processing to semiconductor devices by Intermolecular, Inc. of San Jose, Calif., employing their High-Productivity Combinatorial™ (HPC™) technology and various devices and procedures related thereto. Such technologies also are known as high-throughput combinatorial technology or combinatorial technology. For economy of language we refer generally to such combinatorial techniques as HPC.
HPC processing typically involves isolating numerous regions on the surface of a semiconductor wafer (“wafer”) and processing these isolated regions pursuant to a plurality of different processing protocols. Isolation of these distinct regions has conventionally required the use of a cell that contacts the surface of the wafer, inside which the processing can occur without interference or contamination from other cells. However, contact with the wafer is a dangerous procedure that can easily result in damage to the wafer, or cause particles to be left on the wafer, both of which may affect device performance, especially as semiconductor circuit components become ever smaller and thus more susceptible to small disturbances in or on the wafer. Therefore, noncontact sealing and isolation is an active area of interest in the semiconductor industry.